The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which allows for the doping of ions at a uniform concentration in the channel area of a recess gate.
As semiconductor devices proceed towards a high level of integration, a short channel effect, in which the threshold voltage of a transistor is quickly reduced due to a decrease in the channel length of the transistor, has been observed. In order to remedy this problem, various methods for manufacturing semiconductor devices having various recess channels that are capable of securing an effective channel length have been attempted. As these semiconductor devices have proceeded towards higher levels of integration, research has been directed towards a method for defining a bulb type groove in a recess gate forming area so as to further increase an effective channel length. The bulb type recess gate has advantages including an improved DIBL (drain induced barrier lowering) characteristic.
Hereinbelow, a conventional method for manufacturing a semiconductor device having a bulb type recess gate will be schematically described.
A trench is defined in a semiconductor substrate by etching the element isolation region of the semiconductor substrate. An insulation layer is then deposited in the trench to fill the trench, thereby forming an element isolation structure for delimiting the active region of the semiconductor substrate. Wells are formed by implementing an ion implantation process for the semiconductor substrate (which is formed with the element isolation structure). A recess gate forming area is anisotropically etched in the active region of the semiconductor substrate (which is delimited by the element isolation structure) to define a vertical groove. An oxide layer is then formed on the overall surface of the semiconductor substrate including the vertical groove.
A passivation layer is formed for exposing the bottom surface of the vertical groove by removing a portion of the oxide layer which is formed on the bottom surface of the vertical groove. Then a portion of the semiconductor substrate on the bottom surface of the vertical groove which is exposed through the passivation layer is isoptripically etched to define a spherical groove. As a result, a bulb type groove including the vertical groove and the spherical groove is defined in the semiconductor substrate.
After removing the passivation layer, a channel ion implantation process is implemented into the semiconductor substrate defined with the bulb type groove. Then, a gate insulation layer, a gate conductive layer, and a hard mask layer are sequentially formed on the semiconductor substrate including the surface of the bulb type groove. These layers are then etched to form a recess gate in the bulb type groove. A source area and a drain area are formed in the semiconductor substrate on both sides of the recess gate.
However, in the conventional semiconductor device having the bulb type recess gate, when the channel ion implantation process is implemented, it is impossible to uniformly dope impurities into the semiconductor substrate in the channel area of the recess gate. More specifically, the impurities cannot be uniformly doped into the semiconductor substrate on the surface of the spherical groove. The concentrations of the impurities that are doped into the semiconductor substrate on the sidewall and the bottom of the spherical groove are different. As a consequence, the threshold voltage of the gate varies depending upon a position on the recess gate, causing a deterioration in the threshold voltage characteristic of the device.